# Design Rule Verification Report

Date: |  | 28/02/2021
Time: |  | 09:54:51
Elapsed Time: |  | 00:00:03
Filename: |  | K:\Work\KNIVD\ELLO\1A\hardware\PCB.PcbDoc
Warnings: |  | 0
Rule Violations: |  | 0

## Summary

Warnings | Count
--- | ---
Total | 0

Rule Violations | Count
--- | ---
Clearance Constraint (Gap=0.3mm) (IsRegion),(All) | 0
Clearance Constraint (Gap=0.2mm) (All),(All) | 0
Short-Circuit Constraint (Allowed=No) (All),(All) | 0
Un-Routed Net Constraint ( (All) ) | 0
Width Constraint (Min=0.2mm) (Max=5mm) (Preferred=0.2mm) (All) | 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.5mm) (Conductor Width=0.25mm) (Air Gap=0.25mm) (Entries=4) (All) | 0
Hole Size Constraint (Min=0.025mm) (Max=25mm) (All) | 0
Hole To Hole Clearance (Gap=0mm) (All),(All) | 0
Minimum Solder Mask Sliver (Gap=-100mm) (All),(All) | 0
Silk To Solder Mask (Clearance=-100mm) (IsPad),(All) | 0
Silk to Silk (Clearance=-100mm) (All),(All) | 0
Net Antennae (Tolerance=1mm) (All) | 0
Height Constraint (Min=0mm) (Max=100mm) (Prefered=2.5mm) (All) | 0
Total | 0